کتاب اصول طراحی قالب (Die Design Fundamentals)

اختصاصی از فی لوو کتاب اصول طراحی قالب (Die Design Fundamentals) دانلود با لینک مستقیم و پر سرعت .

کتاب اصول طراحی قالب (Die Design Fundamentals)، کتابی مفید و کاربردی از آموزش طراحی قالب است، که در این کتاب با اجزای قالب و عملیات انجام شده در قالب ها و همچنین طراحی قالب های خم و برش  آشنا خواهید شد. این کتاب مشتمل بر 285 صفحه، در 20 فصل، به زبان انگلیسی، همراه با تصاویر به ترتیب زیر گردآوری شده است:

Chapter 1: INTRODUCTION TO DIE DESIGN

Chapter 2: CLASSIFICATIONS AND TYPES OF DIES

Chapter 3: THE MATERIAL STRIPS

Chapter 4: THE BLANK

Chapter 5: FOURTEEN STEPS TO DESIGN A DIE

Chapter 6: HOW TO LAY OUT A SCRAP STRIP

Chapter 7: HOW TO DESIGN DIE BLOCKS

Chapter 8: HOW TO DESIGN BLANKING PUNCHES

Chapter 9: HOW TO DESIGN PIERCING PUNCHES

Chapter 10: HOW TO DESIGN PUNCH PLATES

Chapter 11: HOW TO DESIGN PILOTS

Chapter 12: HOW TO DESIGN GAGES

Chapter 13: HOW TO DESIGN FINGER STOPS

Chapter 14: HOW TO DESIGN AUTOMATIC STOPS

Chapter 15: HOW TO DESIGN STRIPPERS

Chapter 16: HOW TO APPLY FASTENERS

Chapter 17: HOW TO SELECT A DIE SET

Chapter 18: DIMENSIONS AND NOTES

Chapter 19: THE BILL OF MATERIAL

Chapter 20: PRESSES AND QUICK DIE-CHANGE

جهت خرید کتاب اصول طراحی قالب (Die Design Fundamentals) به مبلغ فقط 2000 تومان و دانلود آن بر لینک پرداخت و دانلود در پنجره زیر کلیک نمایید.

!!لطفا قبل از خرید از فرشگاه اینترنتی کتیا طراح برتر قیمت محصولات ما را با سایر فروشگاه ها و محصولات آن ها مقایسه نمایید!!

!!!تخفیف ویژه برای کاربران ویژه!!!

با خرید حداقل 10000 (ده هزارتومان) از محصولات فروشگاه اینترنتی کتیا طراح برتر برای شما کد تخفیف ارسال خواهد شد. با داشتن این کد از این پس می توانید سایر محصولات فروشگاه را با 20% تخفیف خریداری نمایید. کافی است پس از انجام 10000 تومان خرید موفق عبارت درخواست کد تخفیف و ایمیل که موقع خرید ثبت نمودید را به شماره موبایل [phone] ارسال نمایید. همکاران ما پس از بررسی درخواست، کد تخفیف را به شماره شما پیامک خواهند نمود.

کتاب VHDL modular design and synthesis of cores and systems

اختصاصی از فی لوو کتاب VHDL modular design and synthesis of cores and systems دانلود با لینک مستقیم و پر سرعت .

VHDL modular design and synthesis of cores and systems

By Zainalabedin Navabi

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ترجمه عنوان:

VHDL طراحی مدولار و سنتز هسته و سیستم های

موضوع کتاب:

زبان توصیف سخت افزار VHDL

سال:2011

ناشر:McGraw Hill Professional

ویرایش:3rd ed

صفحه:1 electronic text (xviii, 531 p. : ill. : PDF file

زبان:انگلیسی

شابک/ISBN:0-07-150892-9, 0-07-147545-1, 9780071508926

 

فهرست:

 

1 Digital System Design Automation with VHDL ...........................1
1.1 Abstraction Levels..................................................................2
1.2 System Level Design Flow.....................................................3
1.2.1 Hardware/Software Partitioning ......................................3
1.2.2 Hardware Part ...................................................................4
1.2.3 Software Part .....................................................................5
1.3 RTL Design Flow....................................................................5
1.3.1 Design Entry ......................................................................6
1.3.2 Testbench in VHDL ...........................................................7
1.3.3 Design Validation ..............................................................8
1.3.4 Compilation and Synthesis .............................................10
1.3.5 Timing Analysis ...............................................................13
1.3.6 Post-Synthesis Simulation ..............................................14
1.3.7 Hardware Generation......................................................14
1.4 VHDL....................................................................................14
1.4.1 VHDL Initiation...............................................................14
1.4.2 Existing Languages .........................................................15
1.4.3 VHDL Requirements .......................................................17
1.4.4 The VHDL Language.......................................................20
1.5 Summary ..............................................................................21
Problems.............................................................................................21
Suggested Reading.............................................................................22
2 RTL Design with VHDL ................................................................23
2.1 Basic Structures of VHDL ...................................................24
2.1.1 Entities and Architectures ..............................................25
2.1.2 Entity-Architecture Outline............................................27
2.1.3 Entity Ports......................................................................28
2.1.4 Signals and Variables......................................................29
2.1.5 Logic Value System..........................................................31
2.1.6 Resolutions .......................................................................32
2.2 Combinational Circuits........................................................33
2.2.1 Gate Level Combinational Circuits ................................34
2.2.2 Gate Level Synthesis .......................................................36
2.2.3 Descriptions by Use of Equations ...................................38
2.2.4 Instantiating Other Modules ..........................................43
2.2.5 Synthesis of Assignment Statements .............................44
2.2.6 Descriptions with Sequential Flow.................................45
2.2.7 Combinational Rules .......................................................49
2.2.8 Bussing .............................................................................49
2.2.9 Synthesizing Procedural Blocks......................................50
2.3 Sequential Circuits ..............................................................52
2.3.1 Basic Memory Elements at the Gate Level....................52
2.3.2 Memory Elements Using Procedural Statements .........54
2.3.3 Flip-flop Synthesis...........................................................57
2.3.4 Registers, Shifters and Counters....................................59
2.3.5 Synthesis of Shifters and Counters ................................61
2.3.6 State Machine Coding .....................................................62
2.3.7 State Machine Synthesis.................................................64
2.3.8 Memories ..........................................................................65
2.4 Writing Testbenches ............................................................65
2.5 Synthesis Issues ...................................................................68
2.6 VHDL Essential Terminologies...........................................68
2.6.1 Design...............................................................................68
2.6.2 Analysis ............................................................................68
2.6.3 Library..............................................................................69
2.6.4 Standard Packages ..........................................................69
2.6.5 Elaboration.......................................................................70
2.6.6 Event Driven Simulation ................................................70
2.6.7 Concurrency .....................................................................70
2.6.8 Concurrent Bodies ...........................................................70
2.6.9 Sequentiality ....................................................................70
2.6.10 Sequential Bodies ............................................................71
2.6.11 VHDL Objects and Classes .............................................71
2.6.12 Real Time .........................................................................72
2.6.13 Delta Delay.......................................................................72
2.6.14 Scheduling........................................................................73
2.6.15 Resolution.........................................................................73
2.6.16 Code Formal .....................................................................73
2.7 Summary ..............................................................................73
Problems.............................................................................................73
Suggested Reading.............................................................................76
3 VHDL Constructs for Structure and Hierarchy Descriptions...77
3.1 Basic Components................................................................77
3.1.1 Basic Model ......................................................................78
3.2 Component Instantiations...................................................80
3.2.1 Direct Instantiation .........................................................81
3.2.2 Component Instantiation ................................................81
3.3 Iterative Networks ...............................................................84
3.3.1 Multi-bit Vectors..............................................................85
3.3.2 Multi-instance Generations ............................................85
3.3.3 Simplified Generations....................................................87
3.4 Binding Alternatives............................................................87
3.5 Association Methods ............................................................89
3.6 Generic Parameters .............................................................90
3.6.1 Using Generic Default Values.........................................91
3.6.2 Generic Map Aspect.........................................................92
3.6.3 Generic Association List..................................................93
3.7 Design Configuration ...........................................................94
3.7.1 Basic Configuration Declaration.....................................94
3.7.2 Incremental Configuration..............................................96
3.7.3 Configuring Nested Components....................................97
3.7.4 Indexing Block Configurations .......................................99
3.7.5 Instantiating a Design Unit..........................................100
3.8 Design Simulation..............................................................101
3.9 Summary ............................................................................102
Problems...........................................................................................103
Suggested Reading...........................................................................104
4 Concurrent Constructs for RT Level Descriptions .................105
4.1 Concurrent Signal Assignments .......................................105
4.1.1 Simple Assignments ......................................................106
4.1.2 Conditional Signal Assignment ....................................107
4.1.3 Selected Signal Assignment..........................................109
4.2 Guarded Signal Assignments............................................111
4.2.1 GUARD Signal and Expression ....................................111
4.2.2 Block Statement.............................................................112
4.2.3 Block Statement Ports...................................................113
4.2.4 Nested Block Statements ..............................................114
4.2.5 Guarded Signals.............................................................115
4.2.6 Timing Disconnections ..................................................118
4.3 Summary ............................................................................120
Problems...........................................................................................120
Suggested Reading...........................................................................122
5 Sequential Constructs for RT Level Descriptions ..................123
5.1 Process Statement..............................................................123
5.1.1 Declarative Part of a Process ........................................124
5.1.2 Statement Part of a Process..........................................125
5.1.3 Process Sensitivity List .................................................127
5.1.4 Postponed Processes ......................................................129
5.1.5 Passive Processes...........................................................131
5.2 Sequential Wait Statements .............................................132
5.3 VHDL Subprograms...........................................................135
5.3.1 Function Definition........................................................135
5.3.2 Procedure Definition......................................................137
5.3.3 Language Aspects of Subprograms...............................140
5.3.4 Nesting Subprograms....................................................140
5.4 VHDL Library Structure ...................................................143
5.4.1 Creating Libraries .........................................................143
5.4.2 Using Libraries ..............................................................144
5.5 Packaging Utilities and Components ...............................144
5.5.1 A Package of Utilities ....................................................145
5.5.2 A Package of Components .............................................147
5.6 Sequential Statements.......................................................150
5.6.1 If Statement ...................................................................150
5.6.2 Loop Statement..............................................................151
5.6.3 Case Statement..............................................................153
5.6.4 Assertion Statement ......................................................154
5.7 Summary ............................................................................156
Problems...........................................................................................156
Suggested Reading...........................................................................160
6 VHDL Language Utilities and Packages ..................................161
6.1 Type Declarations and Usage............................................161
6.1.1 Enumeration Type for Multi-Value Logic ....................161
6.1.2 Using Real Numbers......................................................165
6.1.3 Type Conversions...........................................................166
6.1.4 Physical Types................................................................167
6.1.5 Array Declarations.........................................................170
6.1.6 File Type and External File I/O....................................181
6.2 VHDL Operators ................................................................186
6.2.1 Logical Operators...........................................................186
6.2.2 Relational Operators .....................................................187
6.2.3 Shift Operators...............................................................188
6.2.4 Adding Operators...........................................................189
6.2.5 Sign Operators ...............................................................189
6.2.6 Multiplying Operators...................................................189
6.2.7 Other Operators.............................................................190
6.2.8 Aggregate Operation......................................................190
6.3 Operator and Subprogram Overloading ...........................190
6.3.1 Operator Overloading....................................................191
6.3.2 Subprogram Overloading ..............................................193
6.4 Other Types and Type-Related Issues..............................194
6.4.1 Subtypes .........................................................................194
6.4.2 Record Types ..................................................................195
6.4.3 Alias Declaration ...........................................................197
6.4.4 Access Types...................................................................198
6.4.5 Global Objects ................................................................202
6.4.6 Type Conversions...........................................................203
6.4.7 Standard Nine-Value Logic...........................................204
6.5 Predefined Attributes ........................................................205
6.5.1 Array Attributes ............................................................205
6.5.2 Type Attributes ..............................................................206
6.5.3 Signal Attributes............................................................208
6.5.4 Entity Attributes............................................................213
6.5.5 User-Defined Attributes................................................214
6.6 Standard Libraries and Packages.....................................216
6.6.1 STANDARD Package ....................................................216
6.6.2 TEXTIO Package and ASCII I/O ..................................217
6.6.3 Std_logic_1164 Package.................................................220
6.6.4 Std_logic_arith Package ................................................222
6.7 Summary ............................................................................223
Problems...........................................................................................223
Suggested Reading...........................................................................225
7 VHDL Signal Model ....................................................................227
7.1 Characterizing Hardware Languages...............................227
7.1.1 Timing and Concurrency of Operations .......................227
7.2 Signal Assignments............................................................230
7.2.1 Inertial Delay Mechanism.............................................231
7.2.2 Transport Delay Mechanism.........................................232
7.2.3 Comparing Inertial and Transport...............................232
7.3 Concurrent and Sequential Assignments.........................233
7.3.1 Concurrent Assignments...............................................233
7.3.2 Events and Transactions...............................................234
7.3.3 Delta Delay.....................................................................238
7.3.4 Sequential Placement of Transactions .........................242
7.4 Multiple Concurrent Drivers.............................................255
7.4.1 Resolving between Multiple Driving Values................255
7.4.2 Resolutions with Guarded Assignments ......................262
7.4.3 Resolving INOUT Signals .............................................266
7.4.4 Standard Resolution ......................................................268
7.5 Summary ............................................................................268
Problems...........................................................................................269
Suggested Reading...........................................................................272
8 Hardware Cores and Models.....................................................273
8.1 Synthesis Rules and Styles................................................273
8.1.1 Combinational Cores .....................................................274
8.1.2 Sequential Cores ............................................................278
8.1.3 Finite State Machines ...................................................283
8.2 Memory and Queue Structures .........................................292
8.2.1 Generic RAM Core .........................................................292
8.2.2 Synthesizable Push-Pop Stack......................................294
8.2.3 Synthesizable Circular FIFO ........................................297
8.2.4 Dynamic Access Type FIFO ..........................................301
8.3 Arithmetic Cores ................................................................305
8.3.1 Array Multiplier.............................................................306
8.3.2 Carry-Lookahead Adder ................................................308
8.3.3 Synthesizable Booth Multiplier ....................................311
8.4 Components with Separate Control and Data Parts .......314
8.4.1 Sequential Multiplier ....................................................314
8.4.2 von Neumann Computer Model....................................322
8.5 Summary ............................................................................334
Problems...........................................................................................335
Suggested Reading...........................................................................340
9 Core Design Test and Testability .............................................341
9.1 Issues Related to Design Test ...........................................341
9.1.1 Design Test.....................................................................342
9.1.2 Testbench .......................................................................342
9.1.3 Coverage .........................................................................342
9.2 Simple Testbenches............................................................343
9.2.1 Combinational Circuit Testing .....................................343
9.2.2 Sequential Circuit Testing ............................................345
9.3 Testbench Techniques........................................................346
9.3.1 Arbitrary Test Data .......................................................347
9.3.2 Random Test Data .........................................................348
9.3.3 Applying Synchronized Data ........................................351
9.3.4 Synchronized Display of Results...................................352
9.3.5 Displaying Interval Objects ..........................................353
9.3.6 An Interactive Testbench ..............................................355
9.3.7 Queued Data Application ..............................................358
9.3.8 Text File Stimuli and Response....................................359
9.4 Complete System Testing ..................................................361
9.4.1 Multiplier Testing..........................................................361
9.4.2 Processor Testing...........................................................365
9.5 Issues Related to Manufacturing Test..............................371
9.5.1 Manufacturing Test .......................................................371
9.5.2 Fault Model ....................................................................371
9.5.3 Test Generation .............................................................372
9.5.4 Fault Simulation............................................................372
9.5.5 Fault Coverage...............................................................372
9.5.6 Testability ......................................................................372
9.6 Core Test Support Modules ...............................................373
9.6.1 LFSR...............................................................................373
9.6.2 MISR...............................................................................375
9.7 Scan Design and Test Application ....................................377
9.7.1 Starting Design..............................................................377
9.7.2 Scan Insertion ................................................................379
9.7.3 Scan Testbench ..............................................................380
9.7.4 Top Level Tester ............................................................382
9.8 Memory BIST .....................................................................383
9.8.1 Memory BIST Architecture...........................................383
9.8.2 Test Session....................................................................385
9.8.3 BIST Controller..............................................................386
9.8.4 BIST Structure...............................................................386
9.8.5 BIST Tester ....................................................................388
9.9 Summary ............................................................................389
Problems...........................................................................................389
Suggested Reading...........................................................................393
10 Design, Test and Application of a Processor Core ................395
10.1 Design of SAYEH Processor Core .....................................395
10.1.1 Details of Processor Functionality................................396
10.1.2 SAYEH Datapath...........................................................399
10.2 SAYEH VHDL Description................................................401
10.2.1 Data Components ..........................................................401
10.2.2 SAYEH Datapath...........................................................409
10.2.3 SAYEH Controller .........................................................412
10.2.4 Complete SAYEH Processor..........................................418
10.3 SAYEH Testbench / Assembler / Memory Model.............419
10.3.1 Top Level VHDL Testbench ..........................................420
10.3.2 Memory Model................................................................421
10.3.3 Assembler.......................................................................422
10.3.4 Memory Read .................................................................424
10.3.5 Memory Write ................................................................425
10.3.6 Memory File Handling ..................................................426
10.3.7 Sorting Test Program ....................................................427
10.4 SAYEH as an Embedded Processor Core .........................428
10.4.1 Embedded Core Based Design ......................................428
10.4.2 Filter Design ..................................................................429
10.4.3 Core Based Architecture ...............................................430
10.4.4 FIR Program ..................................................................430
10.4.5 FIR Memory and IO Maps ............................................432
10.4.6 Filter Software ...............................................................433
10.5 Summary ............................................................................435
Problems...........................................................................................436
Suggested Reading...........................................................................437
APPENDIXES
A VHDL Keywords .........................................................................439
B VHDL Language Grammar.........................................................441
C VHDL Standard Packages .........................................................461
C.1 STANDARD Package.........................................................461
C.2 TEXTIO Package................................................................463
D STD_LOGIC_1164 Package .......................................................467
E STD_LOGIC_TEXTIO Package ..................................................479
F STD_LOGIC_ARITH Package ....................................................481
G STD_LOGIC_SIGNED.................................................................497
H STD_LOGIC_UNSIGNED............................................................503
I math_real Package.....................................................................509
Index.....................................................................................................523

کتاب Fundamentals of Heat Exchanger Design

اختصاصی از فی لوو کتاب Fundamentals of Heat Exchanger Design دانلود با لینک مستقیم و پر سرعت .

Fundamentals of Heat Exchanger Design

By Ramesh K. Shah, Dusan P. Sekulic

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ترجمه عنوان:

اصول طراحی مبدل های حرارتی

موضوع کتاب:

Technique

سال:2002

ناشر:Wiley

ویرایش:1

فرمت : PDF

صفحه:750

زبان:انگلیسی

شابک/ISBN:0471321710, 9780471321712

 

• فهرست کتاب

Cover......Page 1
Fundamentals of Heat Exchanger Design......Page 3
©......Page 4
Contents......Page 5
Preface......Page 14
NOMENCLATURE......Page 18
1 Classification of Heat Exchangers......Page 32
2 Overview of Heat Exchanger Design Methodology......Page 109
3 Basic Thermal Design Theory for Recuperators......Page 128
4 Additional Considerations for Thermal Design of Recuperators......Page 263
5 Thermal Design Theory for Regenerators......Page 339
6 Heat Exchanger Pressure Drop Analysis......Page 409
7 Surface Basic Heat Transfer and Flow Friction Characteristics......Page 456
8 Heat Exchanger Surface Geometrical Characteristics......Page 594
9 Heat Exchanger Design Procedures......Page 632
10 Selection of Heat Exchangers and Their Components......Page 704
11 Thermodynamic Modeling and Analysis......Page 766
12 Flow Maldistribution and Header Design......Page 840
13 Fouling and Corrosion......Page 894
Appendix A: Thermophysical Properties......Page 937
Appendix B: ?-NTU Relationships for Liquid-Coupled Exchangers......Page 942
Appendix C: Two-Phase Heat Transfer and Pressure Drop Correlations......Page 944
Appendix D: U and CUA Values for Various Heat Exchangers......Page 951
General References on or Related to Heat Exchangers......Page 957
Index......Page 962

Fiberglass Pipe Design:1996

اختصاصی از فی لوو Fiberglass Pipe Design:1996 دانلود با لینک مستقیم و پر سرعت .

170 صفحه pdf

Fiberglass Pipe Design:1996

Manual of Water Supply Practices

American Water Works Association

دانلود کتاب M Bruneau Ductile Design of Steel Structures

اختصاصی از فی لوو دانلود کتاب M Bruneau Ductile Design of Steel Structures دانلود با لینک مستقیم و پر سرعت .

نام کتاب : Ductile Design of Steel Structures

نویسنده : Michel Bruneau  و  Chia-Ming Uang  و  Rafael Sabelli

ویرایش : 2

سال انتشار : 2011

فرمت : PDF

تعداد صفحه : page 920

کیفیت : OCR

انتشارات : McGraw-Hil

زبان:انگلیسی

توجه: در صورت هرگونه مشکل در روند خرید و دریافت فایل از طریق بخش پشتیبانی در سایت مشکل خود را اعلام کنید  

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